The Boundary Scan Technology

What is boundary scan?

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Boundary scan layout on a board

Boundary scan is a method for testing interconnects (thin wire lines) on printed circuit boards or sub-blocks inside an integrated circuit.

The Joint Test Action Group (JTAG) developed a specification for boundary scan testing that was standardized in 1990 as the IEEE Std. 1149.1-1990. In 1994, a supplement that contains a description of the Boundary Scan Description Language (BSDL) was added which describes the boundary-scan logic content of IEEE Std 1149.1 compliant devices. Since then, this standard has been adopted by electronic device companies all over the world. Boundary scan is nowadays mostly synonymous with JTAG.

JTAG or boundary scan was developed to address the "loss of physical access" problems that occur as a result of implementing new packaging technologies. Since its standardization (IEEE 1149.1) boundary scan usage (also known as JTAG) has expanded and evolved into something more like a communications protocol running within an electronic system. In this way, it is similar to the Internet -- which allows you to access all kinds of information. Boundary scan allows you to access all kinds of design and test structures.

    Those structures help you to:
  • Debug and test boards
  • Program devices
  • Diagnose hardware problems
JTAG boundary-scan tools help solve interconnect test problems, and enable CPLD/FPGA Programming and Flash Programming. Boundary scan delivers this functionality because it can be used to access the "internals" of a:
* Device -- to run Built-In Self-Test (BIST)
* Board -- to verify proper assembly
* System -- to help configure a system

    So boundary scan/JTAG gives you the ability to test a:
  • Device and access internal scan
  • Board and program devices
  • System and verify assembly of boards to daughter cards, multichip modules (MCMs) and to other boards on the backplane

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